1. Field of the Invention
This invention relates generally to an improved integrated circuit, very high speed static memory cell which utilizes complementary MOS transistors and silicon on sapphire technology.
2. Description of the Prior Art
A conventional memory cell which has been fabricated from complementary metal oxide simiconductor (CMOS) transistor devices has been known to include, for example, BIT and BIT data bus lines, an address line to select from the memory the location of a particular memory cell, and a sense circuit interface including a memory output driver which has utilized both the BIT and BIT data buses. Consequently, the conventional memory cell has heretofore been relatively symmetrical in design in order to rapidly discharge either of the BIT or BIT input buses. Therefore, transistor devices which are associated with the BIT bus have been chosen to have as wide a channel as those respective transistor devices which are associated with the BIT bus. This has resulted in relatively larger inherent capacitances which must first be charged when addressing the cell in order to read out data. Thus, the read operation is undesirably slowed. At the same time, the relatively wide channels of the transistor switches and the design restraints imposed thereby result in increased space requirements and, therefore, increased production costs.